1. Field of the Invention
This invention relates to a switching device for select-switching the connection between a voltage source and a power-supplied device.
2. Description of the Related Art
As a conventional means for selectively switching an any source from a plurality of voltage sources in an individual semiconductor device or integrated circuit, where one of two kinds of input voltages having different magnitudes is selected as an output voltage, there is a previously known supplied voltage switching circuit in which even if the voltage applied to a first input terminal becomes lower than the voltage applied to a second input terminal, an overcurrent is prevented from passing through a transistor internally provided (for example, see Patent Reference 1).
Further, like PROM, where a plurality of power sources having different voltage levels in operation are used by switching inside a semiconductor device, there is a known power source switching circuit which is difficult to form a current path and can switch the power source with no voltage drop (see Patent Reference 2).
Patent Reference 1: JP-A-2000-124780
Patent Reference 2: Japanese Patent No. 3148454
The problems to be solved for the above prior arts will be explained below. In the prior arts, a P-channel MOS or an N-channel MOS transistor is referred to as PMOS or NMOS transistor, respectively. For the gate-source voltage in them, the source electrode is located at a reference voltage, and for the other voltage values, the grounding terminal is located at the reference voltage=0 V.
First, FIG. 12 explains an embodiment of the above Patent Reference 1. This embodiment presented a problem that unless a voltage source voltage VDDsel of a switching control logic inverter is kept so as to be not lower than a voltage source voltage VDD1 or VDD2, the voltage source on the interrupted side becomes conductive.
Specifically, assuming that with respect to two enhancement type PMOS transistors Tr11 and Tr12, their voltage source input terminal 1 side or 2 side serves as a source electrode and their voltage source output terminal 4 side serves as a drain electrode; and further the source voltage of Tr11 is Vs11, the gate voltage thereof is Vg11, the source voltage of Tr12 is Vs12 and the gate voltage thereof is Vg12, for the voltage source input terminal 1 or 2, in order to place either one of the P-channels of these transistors in an interrupted state, the following condition is required.(Vg11−Vs11)>(gate-source threshold voltage of Tr11)  (1)(Vg12−Vs12)>(gate-source threshold voltage of Tr12)  (2)
Since the above source voltage Vs11 or Vs12 is equal to the voltage source voltage VDD1 or VDD2, respectively, by substitution, the following condition is required.(Vg11−VDD1)>(gate-source threshold voltage of Tr11)  (3)(Vg12−VDD2)>(gate-source threshold voltage of Tr12)  (4)
Now, where the output of the switching control logic inverter for controlling the above transistors ideally changes from a grounding voltage to the voltage source voltage VDDsel of the switching control logic inverter, since the gate voltages Vg11 and Vg12 are equal to this voltage source voltage VDDsel, by substitution, the following condition is required.(VDDsel−VDD1)>(gate-source threshold voltage of Tr11)  (5)(VDDsel−VDD2)>(gate-source threshold voltage of Tr12)  (6)
Accordingly, for a general gate-source threshold voltage=(−0.3 to −0.7) V or so, in order to set the interrupting condition for the above transistors, i.e. gate-source voltage=0 V, the following condition is required.(VDDsel−VDD1)≧0 V  (7)(VDDsel−VDD2)≧0 V  (8)
Thus, it was absolutely necessary that in FIG. 12, the voltage source voltage VDDsel of the switching control logic inverter is kept to be not lower than both voltage source voltages VDD1 and VDD2.
This can be attained if the voltage source voltages VDD1 and VDD2 are known, otherwise the voltage source voltage to be interrupted and the above voltage source voltage VDDsel are correlated with each other so as to satisfy the above Equation (7) or (8). However, switch control could not be done between the above voltages VDD1 and VDD2.
Secondly, FIG. 13 shows an example of FIG. 2 in an embodiment of the above Patent Reference 2. This embodiment presents a problem that if the difference between two voltage source voltages exceeds the forward diode voltage of a parasitic diode that is necessarily generated at the interface between the P-channel electrode and N-well of each of enhancement type PMOS transistors T1 and T3, the voltage source on the interrupted side becomes conductive.
Now, it is assumed that a voltage source voltage VB is selected as a voltage source output voltage VX. For simplicity, as shown in FIG. 13, if level changing circuits 12a, 12b in FIG. 2 in the embodiment of the Patent Reference 2 are replaced by equivalent switches 51, 52 for the switched outputs thereof, respectively, the output voltages switched by the equivalent switches 51, 52 are a grounding voltage for the equivalent switch 51 and a voltage source voltage VB for the equivalent switch 52.
Thus, the above transistor T3 and a depression type NMOS transistor T4 become conductive, whereas the above transistor T1 and a depression type NMOS transistor T2 are interrupted.
As explained in the problem that the invention described in the specification of the above Patent Reference 2 is to solve, because of the insufficient interrupting performance of the transistor T2 on the interrupted side, the voltage source output voltage VX (=VB) is reflected on the drain voltage of the transistor T1 through the N-channel of the transistor T2.
Now, as a condition for interrupting the transistor T1, assuming that its source voltage is Vs1, its drain voltage is Vd1 and the forward diode voltage of a parasitic diode Di1 existing between its source electrode and N-well is Vf1, in order that the parasitic diode Di1 is maintained in its reverse-biased state, the following condition is required.(Vs1−Vd1)<Vf1  (9)
Further, the source Vs1 is equal to the voltage source voltage VA and the drain voltage Vd1 is equal to the voltage source output voltage VX (=VB) through the transistors T3 and T4 on the conductive side and the transistor T2 on the incompletely interrupted side. Therefore, by substitution, the following condition is required.(VA−VB)<Vf1  (10)
Namely, if the voltage source voltage VA on the interrupted state is the voltage source output voltage VB by the forward diode voltage Vf1 of the parasitic diode Di1, it was impossible to keep the interrupted state of the voltage source input terminal 1.
The above inconvenience equally occurs also when in FIG. 13, the voltage source input terminal 1 is on the conductive side and the voltage source input terminal 2 is on the interrupted state. For this reason, assuming that the forward diode voltage of a parasitic diode Di3 is Vf3, resultantly, in the relationship between the voltage source voltages VA and VB, the above inconvenience is attributable to the following fact that
switching control could not be done under the following condition:
when the voltage source input terminal 1 is switch-selected,(VA−VB)≧Vf1  (11)
when the voltage source input terminal 2 is switch-selected,(VB−VA)≧Vf3  (12)